As chip capacity continues to increase significantly, the use of field programmable gate arrays (FPGAs) is quickly replacing the use of application specific integrated circuits (ASICs). An ASIC is a specialized integrated circuit that is designed for a particular application and can be implemented as a specialized microprocessor. Notably, a FPGA is a programmable logic device (PLD) that has an extremely high density of electronic gates as compared to an ASIC. This high gate density has contributed immensely to the popularity of FPGA devices. Notably, FPGAs can be designed using a variety of architectures that can include user configurable input/output blocks (IOBs), and programmable logic blocks having configurable interconnects and switching capability. In some instances, a programmable logic device may include devices that are partially programmable.
The advancement of computer chip technology has also resulted in the development of embedded processors and controllers and even embedded networks having multiple linked devices. An embedded processor or controller can be a microprocessor or microcontroller circuitry that has been integrated into an electronic device as opposed to being built as a standalone module or “plugin card.” Advancement of FPGA technology has led to the development of FPGA-based system-on-chip (SoC) and network-on-chip (NoC) including FPGA-based embedded processor SoCs. A SoC is a fully functional product having its electronic circuitry contained on a single chip. While a microprocessor chip requires ancillary hardware electronic components to process instructions, SoC would include all required ancillary electronics. As platform architectural forms, SoC and NoC are nominally understood to include at least one processor-element. An obvious conceptual extension is instancing of multiple processor elements coupled to each other via a bus (SoC) or network (NoC). A simple example is a cellular telephone SoC that includes a microprocessor, encoder, decoder, digital signal processor (DSP), RAM and ROM, (e.g., two processing elements are part of the system). In this context, processing elements are not restricted to microprocessor; for example RISC (reduced instruction set computer or controller), DSP, Micro-Controller, and cyclostatic processing engines are all allowed.
In order for device manufacturers to develop FPGA-based SoCs or FPGA-based embedded processor SoCs, it is necessary for them to acquire intellectual property rights for system components and/or related technologies that are utilized to create the FPGA-based SoCs. These system components and/or technologies are called cores or Intellectual Property (IP) cores. An electronic file containing system component information can typically be used to represent the core. A device manufacturer will generally acquire several cores that are integrated to fabricate the SoC. More generically, the IP cores can form one or more of the processing modules in an FPGA-based SoCs. The processing modules can either be hardware or software based.
Notwithstanding advantages provided by using FPGA-based SoCs, the development of these SoCs can be very challenging. One of the challenges includes communication among multiple hardware and software processors embedded in a FPGA-based SoC. Typically, such communication occurs over a bus. Unfortunately, bus-based communications performance is fundamentally limited by bandwidth-sharing and arbitration overhead. Therefore, several clock cycles may be required for simple communication among processing modules. Furthermore, type dependencies are not easily supported in the bus communication link physical layer. Network-on-Chip (NoC) is one means by which these limitations may be overcome. However, NoC is also accompanied by relatively high complexity and resource utilization.
A partially reconfigurable-SWITCH (pr-SWITCH) has been proposed as architectural basis for a Network-on-Chip interconnect fabric, alternative to traditional BUS/Platform interconnect. In this context, pr-SWITCH is understood to include partially reconfigurable crossbar and Clos-Switch constructs. Standard crossbar hardware architecture includes a multiplexer bank capable of supporting N-concurrent source-to-sink interconnects. The partially reconfigurable version implements some multiplexer subset capable of supporting M<N concurrent interconnects based upon an applied partial configuration bitstream. Any subset of all possible cross-connections may then be established with successive application of characteristic partial bitstreams, based upon combination of demand-driven partial reconfiguration and multiplexer control mechanisms. In similar fashion, partially reconfigurable Clos-Switch constructs implement reduced multi-layer multiplexer banks collectively spanning all supported K-of-N interconnects. Stated differently, the partially reconfigurable Clos-Switch implements a given K-of-N architecture in form of some spanning-set of partial bitstreams corresponding to smaller Clos-Switch structures. Note, in both cases, multiplexer inputs may be structurally reduced with a concomitant increase of the set of partial bitstreams needed to span all possible connections. At the point where the number of multiplexer inputs is reduced to one, all connections devolve to unitary cross-connections, and associated multiplexer control is eliminated. Major advantages of such pr-SWITCH constructs include reduction of; (1) hardware logic, (2) multiplexer control envelope, and (3) interconnect resource requirements. These advantages are relevant to consideration of pr-SWITCH-based Network-on-Chip. However, additional problems then emerge in form of; (1) average bandwidth that might be supported at any specified source-to-sink connection, (2) bandwidth loss due to partial reconfiguration overhead, and (3) complexity associated with implementation of a network access protocol in combination with partial reconfiguration and multiplexer controls. It would be desirable to have a method and system for enabling a pr-SWITCH-based Network-on-Chip in the context of programmable logic or FPGAs, and that further overcomes the described problems.